By Deepak A. Mathaikutty
This state of the art source deals electrical/computer engineers an in-depth realizing of metamodeling ways for the reuse of highbrow homes (IPs) within the kind of layout or verification elements. The ebook covers the basic concerns linked to speedy and potent integration of reusable layout elements right into a system-on-a-chip (SoC) to accomplish speedier layout turn-around time. additionally, it addresses key elements concerning using reusable verification IPs for a 'write as soon as, use time and again' verification process - one other powerful technique that could reach a quicker product layout cycle.
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Additional info for Metamodeling-Driven IP Reuse for SoC Integration and Microprocessor Design
Shukla, “MCF: A Metamodeling based Component Composition Framework — Composing SystemC IPs for Executable System Models,” IEEE Transactions on Very Large Integration (VLSI) Systems, Vol. 16, No. 7, July 2008, pp. 792–805.  D. Mathaikutty and S. Shukla, “Mining Metadata for Composability of IPs from SystemC IP Library,” Design Automation for Embedded Systems, Vol. 12, No. 1-2, 2008, pp. 63–94. html. org/. com/. org/. com/.  R. Goering, “IEEE Catches the Spirit of IP Reuse,” EE Times, June 2006.
5 PROBLEM STATEMENT The overarching problem is to enable design and verification for SoCs and microprocessors, which promote effective reuse of design IP as well as verification IP leveraging metamodeling techniques. On the design front, we want to enable rapid design space exploration during the design of SoCs by providing languages, tools, and techniques for building fast simulation models by automating reuse from a library of SystemC IPs. On the verification front, we want to enable verification of the architecture and microarchitecture implementations of a processor by providing languages, tools, and techniques for creating system-level models for the relevant parts of the processor and automatically generating verification collaterals such as functional simulators, test generators, and coverage constraints by reusing these models.
61] S. Kodakara, D. Mathaikutty, A. Dingankar, S. Shukla, and D. Lilja, “A Probabilistic Analysis For Fault Detectability of Code Coverage Metrics,” Proceedings of the 7th International Workshop on Microprocessor Test and Verification (MTV’06), December 2006.  M. F. Lau and Y. T. Yu, “An Extended Fault Class Hierarchy for Specification-Based Testing,” ACM Transactions on Software Engineering and Methodology, Vol. 14, No. 3, 2005, pp. 247–276. Chapter 2 Background In this chapter, we introduce the background material necessary to better appreciate the content of this book.