Broadband Opto-Electrical Receivers in Standard CMOS (Analog by Carolien Hermans

By Carolien Hermans

This e-book opens with the fundamentals of the layout of opto-electronic interface circuits. The textual content keeps with an in-depth research of the photodiode, transimpedance amplifier (TIA) and proscribing amplifier (LA). to entirely describe mild detection mechanisms in silicon, first a one-dimensional and moment a two-dimensional version is built. All fabric is experimentally demonstrated with a number of CMOS implementations, with finally a completely built-in Gbit/s optical receiver front-end together with photodiode, TIA and l. a..

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Extra resources for Broadband Opto-Electrical Receivers in Standard CMOS (Analog Circuits and Signal Processing)

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A group of bits is replaced by another, slightly larger group of bits, such that the average mark density becomes 50 % and DC balance is established. For example, in the 8B10B code, 8-bit groups are replaced with 10-bit patterns using a look-up table. 3 Binary Data Formats 1 2 3 n−1 Clock 19 Data out n Data in Fig. 5. An n-bit shift register for the generation of a 2n − 1 prbs pattern. 1 0 0 1 1 0 1 1 0 1 0 0 0 1 0 1 1 0 1 0 1 continuous mode time 1 0 0 1 1 0 1 1 burst mode time Fig. 6. Continuous mode versus burst mode data.

If the activity is low, the DC value drifts arbitrarily close to the zero level. 2). The receiver front-ends described in this work are designed for continuous mode transmission. To study the effects of circuit and/or system non-idealities on random data, the eye diagram is often used. Such a diagram folds all of the bits into a short interval, for example two bits wide. The total waveform is first cut into two-bit segments. Next, all these segments are superimposed, displaying 20 2 Optical Receiver Fundamentals 0 0 0/1 1 1 1/0 0 1 0/1 1 0 1/0 Fig.

Such a large intrinsic layer thickness requires a severe reduction of the epitaxial layer concentration to obtain a spreading of the electric field over the entire intrinsic zone. However, this would destroy the bipolar transistor performance. Therefore, process modifications are needed to optimize the performance of both the integrated photodiode (which needs a thick, lowly doped intrinsic layer) and the bipolar transistor (which needs a thin, higher doped n-collector). 5 µm BiCMOS technology that combines highspeed transistors with an integrated PIN photodiode is described.

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